1. Field of the Invention
This invention relates generally to an apparatus for performing single-error correction and double-error detection (SEC-DED) and, more particularly, to a large scale integrated circuit which may be used in multiples to implement SEC-DED. Eight such large scale integrated circuit parts in combination with eight MSI 8-bit parity generators of the type which are commercially available are sufficient for the generation, correction and detection of an 80-bit code word (72 bits of data+8 check bits).
2. Description of the Prior Art
An industry need exists for a large scale integrated circuit implementation of a double-error detecting, single-error correcting (distance four code) logic network. Of particular importance is low propagation delay, with a goal of no more than 60 nsec added to the memory access time for the error detection and correction (EDAC) function. To be marketable, the network should be partitioned into no more than two part types with no more than forty pins per package. It is assumed that transistor-transistor-logic (TTL) compatibility is necessary, although interconnections between packages might employ higher levels as required.
Motorola has approached a similar problem by developing, as part of their MECL 10,000 series medium scale integration parts, an MC10162 and MC10193 which perform an EDAC function. This arrangement, however, cannot handle 9-bit bytes and requires additional circuitry to decode the syndrome, correct each data bit and generate parity.